library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity imagerTestbench is
end imagerTestbench;

architecture test of imagerTestbench is

  component MT9V032 is
    port(TW_Clk : in std_logic;
       TW_Data : inout std_logic);
  end component;

  signal clk,data,dir,buf,clk100k : std_logic:='1';

begin
  
  imager: MT9V032 port map(clk,data);
  clk100k<=not clk100k after 5us;
  
  process (data,dir)
	begin
	  if Dir = '1' then
      buf <= Data;
	  end if;
	end process;
	
	process (dir,buf)
	begin
	  if dir = '0' then
	    data <= buf;
	  else
	    data <= 'Z';
	  end if;
	end process;
	
	TEST:process
	begin
	  wait for 10 ns; --initial state check
	  dir<='0';
	  clk<='0';
	  wait for 10 ns;
	  buf<='0';
	  clk<='1';
	  wait for 10 ns;
	  dir<='1';
	  buf<='Z';
	  clk<='0';
	  wait for 10 ns;
	  
	  wait;
  end process;
  
end test;

architecture test2 of imagerTestbench is

  component MT9V032 is
    port(TW_Clk : in std_logic;
       TW_Data : inout std_logic);
  end component;

  signal clk,data,dir,buf,clk100k : std_logic:='1';

begin
  
  imager: MT9V032 port map(clk,buf);
  clk100k<=not clk100k after 5us;
  
  
	
	TEST:process
	begin
	  clk<='1';
	  dir<='0';
	  buf<='1';
	  wait for 100 ns;
	  wait until rising_edge(clk100k);
	  clk<=clk100k;
	  --start bit
	  wait for 3 us;
	  buf<='0';
	  wait for 2 us;
	  wait for 5 us;
	  buf<='1';	  
	  wait for 10 us;
	  buf<='0';
	  wait for 10 us;
	  buf<='1';
	  wait for 10 us;
	  buf<='1';
	  wait for 10 us;
	  buf<='0';
	  wait for 10 us;
	  buf<='0';
	  wait for 10 us;
	  buf<='0';
	  wait for 10 us;
	  buf<='0';
	  wait for 10 us;
	  dir<='1';
	  wait for 10 us;
  end process;
  
end test2;